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General
Register
This CPU has eight 16-bit general registers. And the AX,BX,CX,DX
can be subdivided into two 8-bit register (AH,AL,BH,
BL,CH,CL,DH,DL). The functions
of these registers are described as follows.
- AX : Word Divide , Word
Multiply, Word I/O operation.
- AH : Byte Divide , Byte Multiply, Byte I/O
, Decimal Arithmetic, Translate operation.
- AL : Byte Divide , Byte Multiply
operation.
- BX : Translate operation.
- CX : Loops, String operation
- CL : Variable Shift and Rotate operation.
- DX : Word Divide ,
Word Multiply, Indirect I/O operation
- SP : Stack operations (POP, POPA,
POPF, PUSH, PUSHA, PUSHF)
- BP : General-purpose register which can be used
to determine offset address of operands in Memory.
- SI : String operations
- DI : String operations
Segment Register
This CPU has four 16-bit segment registers, CS,
DS, SS, ES. The segment registers contain the base addresses (starting location)
of the memory segments, and they are immediately addressable for code (CS), data
(DS & ES), and stack (SS) memory.
CS (Code Segment) : The CS
register points to the current code segment, which contains instruction to be
fetched. The default location memory space for all instruction is 64K. The initial
value of CS register is 0FFFFh.
DS (Data Segment) : The DS register
points to the current data segment, which generally contains program variables.
The DS register initialize to 0000H.
SS (Stack Segment ) : The SS
register points to the current stack segment, which is for all stack operations,
such as pushes and pops. The stack segment is used for temporary space. The SS
register initialize to 0000H.
ES (Extra Segment) : The ES register
points to the current extra segment which is typically for data storage, such
as large string operations and large data structures. The DS register initialize
to 0000H.
Instruction
Pointer and Status Flags Register
IP (Instruction Pointer) : The
IP is a 16-bit register and it contains the offset of the next instruction to
be fetched. Software can not to direct access the IP register which is updated
by the Bus Interface Unit. It can change, be saved or be restored as a result
of program execution. The IP register initialize to 0000H and the CS:IP starting
execution address is at 0FFFF0H.
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These
flags reflect the status after the Execution Unit is executed.
Bit 15-12
:
Reserved
Bit 11:
OF, Overflow Flag. An arithmetic
overflow has occurred, this flag will be set.
Bit 10 :
DF, Direction
Flag. If this flag is set, the string instructions are increment address process.
If DF is cleared, the string
instructions are decrement address process. Refer
the STD and CLD instructions for how to set and clear the DF flag.
Bit
9 :
IF, Interrupt-Enable Flag. Refer the STI and CLI instructions for
how to set and clear the IF flag.
Set to 1 : The CPU enables the maskable
interrupt request.
Set to 0 : The CPU disables the maskable interrupt request.
Bit 8:
TF, Trace Flag. Set to enable single-step mode for debugging;
Clear to disable the single-step mode. If an application
program sets the
TF flag using POPF or IRET instruction, a debug exception is generated after the
instruction (The
CPU automatically generates an interrupt after each instruction)
that follows the POPF or IRET instruction.
Bit 7:
SF, Sign Flag.
If this flag is set, the high-order bit of the result of an operation is 1,indicating
it is negative.
Bit 6:
ZF, Zero Flag. The result of operation
is zero, this flag is set.
Bit 5:
Reserved
Bit 4:
AF, Auxiliary Flag. If this flag is set, there has been a carry from the low nibble
to the high or a borrow from the high
nibble to the low nibble of the AL
general-purpose register. Used in BCD operation.
Bit 3:
Reserved.
Bit
2:
PF, Parity Flag. The result of low-order 8 bits operation has even
parity, this flag is set.
Bit 1:
Reserved
Bit 0:
CF, Carry Flag. If CF is set, there has been a carry out or a borrow into the
high-order bit of the instruction result.
Address generation
The
Execution Unit generates a 20-bit physical address to Bus Interface Unit by the
Address Generation. Memory is organized in sets of segments. Each segment contains
a 16 bits value. Memory is addressed using a two-component address that consists
of a 16-bit segment and 16-bit offset. The Physical Address Generation figure
describes how the logical address transfers to the physical address.
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